<?xml version="1.0" encoding="utf-8" standalone="yes"?><rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Baleegh Ahmad | IsPri UNSW</title><link>https://ispri-unsw.pages.dev/author/baleegh-ahmad/</link><atom:link href="https://ispri-unsw.pages.dev/author/baleegh-ahmad/index.xml" rel="self" type="application/rss+xml"/><description>Baleegh Ahmad</description><generator>Hugo Blox Builder (https://hugoblox.com)</generator><language>en-us</language><lastBuildDate>Sat, 01 Nov 2025 00:00:00 +0000</lastBuildDate><image><url>https://ispri-unsw.pages.dev/media/icon_hu_65667889a57295f.png</url><title>Baleegh Ahmad</title><link>https://ispri-unsw.pages.dev/author/baleegh-ahmad/</link></image><item><title>FLAG: F inding L ine A nomalies (in RTL code) with G enerative AI</title><link>https://ispri-unsw.pages.dev/filtered_publication/doi-3736411/</link><pubDate>Sat, 01 Nov 2025 00:00:00 +0000</pubDate><guid>https://ispri-unsw.pages.dev/filtered_publication/doi-3736411/</guid><description/></item><item><title>FLAG: F inding L ine A nomalies (in RTL code) with G enerative AI</title><link>https://ispri-unsw.pages.dev/publication/doi-3736411/</link><pubDate>Sat, 01 Nov 2025 00:00:00 +0000</pubDate><guid>https://ispri-unsw.pages.dev/publication/doi-3736411/</guid><description/></item><item><title>VeriGen: A Large Language Model for Verilog Code Generation</title><link>https://ispri-unsw.pages.dev/filtered_publication/doi-3643681/</link><pubDate>Wed, 01 May 2024 00:00:00 +0000</pubDate><guid>https://ispri-unsw.pages.dev/filtered_publication/doi-3643681/</guid><description/></item><item><title>VeriGen: A Large Language Model for Verilog Code Generation</title><link>https://ispri-unsw.pages.dev/publication/doi-3643681/</link><pubDate>Wed, 01 May 2024 00:00:00 +0000</pubDate><guid>https://ispri-unsw.pages.dev/publication/doi-3643681/</guid><description/></item></channel></rss>