B. Ahmad
Latest
- LASHED: LLMs And Static Hardware Analysis for Early Detection of RTL Bugs
- LASHED: LLMs And Static Hardware Analysis for Early Detection of RTL Bugs
- On Hardware Security Bug Code Fixes By Prompting Large Language Models
- On Hardware Security Bug Code Fixes By Prompting Large Language Models
- Benchmarking Large Language Models for Automated Verilog RTL Code Generation
- Benchmarking Large Language Models for Automated Verilog RTL Code Generation
- Examining Zero-Shot Vulnerability Repair with Large Language Models
- Examining Zero-Shot Vulnerability Repair with Large Language Models
- Fixing Hardware Security Bugs with Large Language Models
- Fixing Hardware Security Bugs with Large Language Models
- FLAG: Finding Line Anomalies (in code) with Generative AI
- FLAG: Finding Line Anomalies (in code) with Generative AI
- VeriGen: A Large Language Model for Verilog Code Generation<sup>∗</sup>
- VeriGen: A Large Language Model for Verilog Code Generation<sup>∗</sup>
- Asleep at the Keyboard? Assessing the Security of GitHub Copilot's Code Contributions
- Asleep at the Keyboard? Assessing the Security of GitHub Copilot's Code Contributions
- Don t CWEAT it: Toward CWE analysis techniques in early stages of hardware design
- Don t CWEAT it: Toward CWE analysis techniques in early stages of hardware design
- Don't CWEAT It: Toward CWE Analysis Techniques in Early Stages of Hardware Design
- Don't CWEAT It: Toward CWE Analysis Techniques in Early Stages of Hardware Design
- An empirical cybersecurity evaluation of GitHub Copilot's code contributions
- An empirical cybersecurity evaluation of GitHub Copilot's code contributions